TRF BLD

1 Diagnostic Link

Diagnostics >> System Function >> Acquisition / Pulse Generation >> Data Acquisition

Diagnostics >> Hardware Location >> System Cabinet >> CAM >> Data Acquisition

Figure 1. TRF BLD

2 Purpose

The Trigger and Rotation Functionality (TRF) Board Level Diagnostic (BLD) performs the tests listed below.

3 Components Tested

This board relies heavily on the functionality of the SRF and STIF to perform these tests. Patterns used to validate the memory are selectable and are listed below. The items highlighted in green in the following block diagrams show what has been tested.

4 Requirements

None

5 Block Diagrams

Figure 2. SRF for TRF Block Diagram

Figure 3. TRF Block Diagram

Figure 4. STIF Board Level Diagnostics Block Diagram

6 Test Sequence

Short vs. Long Tests: The short test performs a walking ones and walking zeroes pattern whereas the long test will perform a walking ones, walking zeroes, 0xaaaa, 0x5555, and possibly other patterns. As a result, selecting the long test will generally provide a longer and more exhaustive test. If the problem is highly intermittent then it may be desirable to run a long test.

Click Calculate Time to get an estimate of the time it will take to run the selected diagnostics.

0.TRF serial number verify tests

  1. Registers Initial State Verification

  2. Registers Write Verification

  3. Status Check Tests

  4. PCI to DPR Memory Tests

  5. DPR Semaphore Tests

  6. Semaphore Registers Verification

  7. HPI Data Bus Verification

  8. HPI Functional Verification

  9. HPI to C6X Internal Program Memory Tests

  10. HPI to C6X Internal Data Memory Tests

  11. HPI to DPR Memory Tests

  12. HPI to C6X External SSRAM Memory Tests

  13. C6X Self Tests

  14. Duart Tests

  15. C6X to AGP HPI Interrupt Tests

  16. AGP to C6X HPI Interrupt Tests

  17. McBSP WARP Serial Loopback Test

  18. McBSP SPU Serial Loopback Test

  19. McBSP SPU Serial Loopback Test

  20. Warp External WMI Loop Test

  21. SPU External Loop Test

  22. SPU Trigger Internal Test

  23. SPU External Loop Test

Memory Pattern

  • 0 MINIMUM or Power Up = 0's, F's, and an Address Test (Incrementing values)

  • 1 Short = 0's, F's, A's, 5's and an address test.

  • 2 Medium = 0's, F's, A's, 5's, walking one's, and an address test.

  • 3 Long = 0's, F's, A's, 5's, walking one's, walking 0's, and an address test.

7 Expected Results

Output values are judged pass or fail. In the event of failure, the details of the failure can be found in the GE System Log.

Although, in the case of errors you can click the 1st Error number to see the nature of the error, it is recommended that you view the GE System Log to view all the errors that were recorded.

note:

The Test Options settings should not be changed from their default settings unless instructed to do so by a GE Healthcare engineer. There are very few circumstances when these settings ever need to be changed.

Notice Image
  • notice
  • Prior to scanning, a TPS reset is required.